The Hardware Architecture of EVT4 Electrical Capacitance Tomograph
W.T. Smolik, J. Kryszyn, P. Wróblewski, M. Stosio, T. Olszewski and R. Szabatin
Warsaw University of Technology, Faculty of Electronics and Information Technology, Division of Nuclear and Medical Electronics
Nowowiejska 15/19, Warsaw, Poland W.Smolik@ire.pw.edu.pl
The design of EVT4 multi-channel electrical capacitance tomograph is presented. A new hardware architecture based on distributed control logic and multi-gigabit transmission is proposed. The system consists of analogue measurement boards, data read-out boards and a main board (crate controller). The system is housed in a 19'' 6U Euro crate with a custom middle plane. An analogue board is equipped with 4 transmitter-receiver channels with one ADC per channel. The read-out boards are equipped with Xilinx Spartan-6 programmable logic device programmed using VHDL and assembler language of a PicoBlaze soft processor. The readout-boards are connected to the control board using SATA cables allowing high speed data transfer. The control board contains a Spartan-6 FPGA and ARM Cortex-A8 processor. The control board processor is responsible for communication with the host computer, control of the measurement process and transmission of measurement data. The entire system is controlled from the host computer which is connected to the hardware unit through an Ethernet link. The system can be equipped with up to 8 analogue boards what gives up to 32 channels. The flexibility of the system offers the opportunity to explore different methods of capacitance measurement using different front-end boards. The theoretical data throughput of the hardware enables dynamic imaging with a frame rate of about 10000 frames/s for 32 electrodes.
Keywords capacitance measurement, electrical capacitance tomography, hardware design
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