Parallel Realisation of the Linear Back-projection Algorithm for Capacitance Tomography Using TMS320C6701

Digital Signal Processors

D F Garcia-Nocetti 1, J C Gamio 2 and L A Aguilar 1

1DISCA-IIMAS, Universidad Nacional Autonoma de Mexico, Cto Escolar CU, Mexico, DF, 04510, Mexico

2 Instituto Mexicano del Petroleo, Eje Central L Cardenas 152, Mexico, DF, 07730, Mexico jgamio@imp.mx

ABSTRACT

This work presents a high-performance parallel digital-signal-processor (DSP) architecture for the computation of the linear back-projection (LBP) image reconstruction algorithm used in electrical capacitance tomography. A system based on a PCI-bus compatible co-processor card with four TMS320C6701 DSPs was used. The improvement in global image-reconstruction speed that can be achieved running the LBP algorithm concurrently on 1, 2, 3 and 4 processors is examined. It was found that, with the programming scheme employed, the execution speed increases in an almost linear way with the number of processors, which confirms that the LBP algorithm lends itself well to the use of parallel processing. A performance analysis of the implementation is presented, demonstrating the effectiveness of the algorithm for real-time response.

Keywords Parallel processing, Capacitance tomography, Linear back-projection, Digital signal processor