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International Society for Industrial Process Tomography

5th World Congress on Industrial Process Tomography

A Hardware Accelerator for Electrical Resistance Tomography System

J. Frounchi, K. S. Zamini, H. Taghipour, M. H. Zarifi and H. Soltani

Microelectronic and Microsensor Research Laboratory, Faculty of Electrical and Computer

Engineering, University of Tabriz, Tabriz, Iran, Email:


The goal of the image reconstruction algorithm in an electrical resistance tomography system is to find a conductivity distribution under the ground in a way that nearly the same surface potentials can be measured in those points when the current injected into the ground. The first step in the procedure is to calculate the potential distribution (V) at any node (i, j, k) of the grid due to a point source of current on the surface of the half-space (Forward solving). We have implemented the forward solver architecture on a Virtex-4 LX25 FPGA from Xilinx. The parallel processing and pipelining techniques have been used extensively in this system.The number of occupied slice is 927 so the design occupies only 8% of the FPGA. The computation time of the coupling coefficients for a grid of 13×13×14 nodes is only 48 us using a 50 MHz clock signal on the chip. The same routine on the MATLAB takes about one second. A fair comparison taking into consideration the data precisions of our system and the MATLAB reveals that the speed enhancement of more than X100 can be achieved using our hardware accelerator chip.

Keywords Electrical resistance tomography, FPGA, Hardware accelerator, 3-D resistivity inversion, Dynamically reconfigurable computing platform.

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